There has been an increasing demand for higher power and a higher withstand voltage in power semiconductor devices, each having a power semiconductor chip such as a MOS-FET and an IGBT mounted therein. Various semiconductor chips and packages for the semiconductor chips have been proposed in response to the demand.
In a semiconductor device and a method of manufacturing the same according to the prior art, a semiconductor chip and an external terminal are bonded with a belt of Al (aluminum ribbon) to apply a large current to the semiconductor device with a low resistance, so that an electric resistance at a joint is reduced. In recent years, in order to further reduce a resistance and obtain stable connection, multiple Al ribbons are connected in a stacked manner so as to have an increased cross sectional area.
FIG. 4 shows the connection configuration of an element electrode and an external electrode in a semiconductor device of the prior art.
In FIG. 4, a power semiconductor device 101 has a semiconductor chip 103 mounted on a lead frame 102. On the surface of the semiconductor chip 103, a source electrode 103a is formed. Further, a relatively thin conductive ribbon 105 is provided thereon and is bonded to the source electrode 103a by ultrasonic bonding. Provided on the conductive ribbon 105 is a conductive ribbon 106 larger in thickness than the conductive ribbon 105. The conductive ribbon 106 is bonded to the conductive ribbon 105 by ultrasonic bonding with the conductive ribbon 105 interposed between the conductive ribbon 106 and the source electrode 103a. The other side of the conductive ribbon 106 is similarly bonded by ultrasonic bonding with a conductive ribbon 107 interposed between the conductive ribbon 106 and a lead 108 serving as an external terminal of the lead frame 102 (e.g., see Patent Literature 1).